Robin L. Michael v. Rodney C. Michael : Brief of Appellant

ON APPEAL FROM THE THIRD JUDICIAL DISTRICT COURT IN AND FOR SALT LAKE COUNTY, STATE OF UTAH HONORABLE TIMOTHY R. HANSON, DISTRICT COURT JUDG

NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs

In this paper we propose a novel Content Addressable Memory (CAM) cell, NEMsCAM, based on both Nano-electro-mechanical (NEM) switches and CMOS technologies. The memory component of the proposed CAM cell is designed with two complementary non-volatile NEM switches and located on top of the CMOS-based comparison component. As a use case for the NEMsCAM cell, we design first-level data and instruction Translation Lookaside Buffers (TLBs) with 16nm CMOS technology at 2GHz. The simulations show that the NEMsCAM TLB reduces the energy consumption per search operation (by 27%), write operation (by 41.9%) and standby mode (by 53.9%), and the area (by 40.5%) compared to a CMOS-only TLB with minimal performance overhead.We thank all anonymous reviewers for their insightful comments. This work is supported in part by the European Union (FEDER funds) under contract TIN2012-34557, and the European Union’s Seventh Framework Programme (FP7/2007-2013) under the ParaDIME project (GA no. 318693)Postprint (author's final draft

An Energy-Efficient Design Paradigm for a Memory Cell Based on Novel Nanoelectromechanical Switches

In this chapter, we explain NEMsCAM cell, a new content-addressable memory (CAM) cell, which is designed based on both CMOS technologies and nanoelectromechanical (NEM) switches. The memory part of NEMsCAM is designed with two complementary nonvolatile NEM switches and located on top of the CMOS-based comparison component. As a use case, we evaluate first-level instruction and data translation lookaside buffers (TLBs) with 16 nm CMOS technology at 2 GHz. The simulation results demonstrate that the NEMsCAM TLB reduces the energy consumption per search operation (by 27%), standby mode (by 53.9%), write operation (by 41.9%), and the area (by 40.5%) compared to a CMOS-only TLB with minimal performance overhead

Design and Benchmarking of Hybrid CMOS-Spin Wave Device Circuits Compared to 10nm CMOS

In this paper, we present a design and benchmarking methodology of Spin Wave Device (SWD) circuits based on micromagnetic modeling. SWD technology is compared against a 10nm FinFET CMOS technology, considering the key metrics of area, delay and power. We show that SWD circuits outperform the 10nm CMOS FinFET equivalents by a large margin. The area-delay-power product (ADPP) of SWD is smaller than CMOS for all benchmarks from 2.5× to 800×. On average, the area of SWD circuits is 3.5× smaller and the power consumption is two orders of magnitude lower compared to the 10nm CMOS reference circuits

Variability-Aware Design of Low Power SRAM Memories (Variabiliteitsbewust ontwerp van SRAM geheugens met een zeer laag energieverbruik)

Een laag energieverbruik per bewerking is een van de belangrijkste vereisten bij het ontwerp van draagbare toestellen zoals smartphones. Veelbelovende nieuwe toepassingen zoals intelligente sensoren voor Ambient Intelligence kunnen maar worden verwezenlijkt als het energieverbruik per bewerking nog aanzienlijk daalt.In de meeste toepassingen nemen geheugens een belangrijke plaats in in het totale energieverbruik. Na optimalisatie vertonen typische applicaties een sterke datalokaliteit, zodat het energieverbruik van de relatief kleine geheugens die dicht bij de processor staan vaak dominant is.Dit werk introduceert nieuwe energiezuinigere schakelingen en geheugenorganisaties voor deze relatief kleine SRAM geheugens met een gematigde snelheid. Hierbij wordt expliciet rekening gehouden met de nieuwe uitdagingen die samengaan met de hedendaagse technologieen: lekstromen, grote ongecorreleerde variaties tussen transistoren binnen een chip en de dominante impact van de verbindingsdraden op de performantie.De belangrijkste innovaties zijn een verbeterde bitlijnstructuur, het gebruik van dynamische leesstabiliteit voor de geheugencel, gekalibreerde leesversterkers en een efficientere implementatie van geheugens met meerdere snelheidsmodes dankzij het gebruik van gekalibreerde timing en het selectief verlagen van voedingsspanningen. Deze tekst bespreekt alle belangrijke onderdelen van een SRAM geheugen en kadert de nieuwe technieken in een breed literatuuroverzicht.De nieuwe technieken worden geillustreerd en gevalideerd met twee succesvolle prototype geheugens. Het meest recente prototype is een geheugen met 4K woorden van 32 bits (128Kbit) in een 90nm technologie. Het ondersteunt verschillende werkingsmodes. In de 1.2V mode is de maximale kloksnelheid 850MHz en het totale energieverbruik per operatie is 8.4pJ. In de 0.6V mode is de maximale kloksnelheid 240MHz en het totale energieverbruik per operatie is 2.7pJ. Dit prototype heeft een aanzienlijk lager energieverbruik per operatie dan de andere geheugenontwerpen uit de literatuur voor snelheden tussen 100MHz en 850MHz.1. Introduction 2. Memory Cell 3. Local Memory Matrix 4. Sense Amplifiers 5. Sense Amplifier Calibration 6. Data Transfers 7. Global Control Circuits: Decoder and Timing 8. Prototypes 9. Conclusionsnrpages: 298status: publishe

A low leakage 500MHz 2T embedded dynamic memory with integrated semi-transparent refresh

This paper presents a low-leakage 128 kbit dynamic memory based on a 2T dynamic cell. The design is implemented in a logic 90 nm technology and achieves a low static power consumption of 130 μW and an access time of 2 ns. It has a worst case retention time of 175 μs. This performance is achieved by introducing an optimised hierarchical organisation and peripheral circuits for the read, the write and the refresh operations. A novel writing mechanism for 2T cells using a double phase approach is demonstrated. The area penalty of using short read bitlines is alleviated using a charge transfer sense amplifier (SA). A novel local write sense amplifier (WSA) that can operate as a latch makes it possible to perform the refresh operation at the local level, improving the energy efficiency of the refresh operation. The memory includes an integrated automatic refresh mechanism. Most read and write operations can still be performed during refresh cycles. In cases where the accessed address conflicts with the refresh operation, the memory handles access recovery internally. © 2012 Elsevier Ltd. All rights reserved.status: publishe

A 3.6 pJ/Access 480 MHz, 128 kb On-Chip SRAM With 850 MHz Boost Mode in 90 nm CMOS With Tunable Sense Amplifiers

An extremely low energy per operation, single cycle 32 bit/word, 128 kb SRAM is fabricated in 90 nm CMOS. In the 850 MHz boost mode, total energy consumption is 8.4 pJ/access. This reduces to 3.6 pJ/access in the normal 480 MHz mode and bottoms out at a very aggressive 2.7 pJ/access in the 240 MHz low power mode. Several techniques were combined to obtain these performance numbers. Short buffered local bit lines reduce the impact of the cell read current on memory delay. Extended global bitlines are used which improves delay and energy consumption and which reduces the number of sense amplifiers in the memory to 32. Cell stability and speed issues are avoided by applying selective voltage scaling. Novel, digitally tunable sense amplifiers and a tunable timing circuit cope gracefully with the stochastic variations in the periphery.status: publishe

A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, Ultra Low Leakage Power Memory Using Dynamic Cell Stability and a Dual Swing Data Link.

status: publishe

A Low Leakage 500 MHz 2T Embedded Dynamic Memory With Integrated Semi-transparent Refresh

This paper presents a low-leakage 128 kbit dynamic memory based on a 2T dynamic cell. The design is implemented in a logic 90 nm technology and achieves a low static power consumption of 130 mWand an access time of 2 ns. It has a worst case retention time of 175 ms. This performance is achieved by introducing an optimized hierarchical organization and peripheral circuits for the read, the write and the refresh operations. A novel writing mechanism for 2T cells using a double phase approach is demonstrated. The area penalty of using short read bitlines is alleviated using a charge transfer sense amplifier (SA). A novel local write sense amplifier (WSA) that can operate as a latch makes it possible to perform the refresh operation at the local level, improving the energy efficiency of the refresh operation. The memory includes an integrated automatic refresh mechanism. Most read and write operations can still be performed during refresh cycles. In cases where the accessed address conflictsstatus: publishe